Memory cells of a dynamic random access memory (DRAM) generally include a storage capacitor for storing an electrical charge that represents information to be stored, and an access transistor connected with the storage capacitor. The access transistor includes first and second source/drain regions, a channel connecting the first and second source/drain regions and a gate electrode controlling an electrical current flowing between the first and second source/drain regions. The gate electrode is electrically insulated from the channel by a gate dielectric. The transistor is usually partially formed in a semiconductor substrate, such as a silicon substrate. The portion, in which the transistor is formed, generally is denoted as the active area.
In conventional DRAM memory cell arrays, the gate electrode forms part of a word line. By addressing the access transistor via the corresponding word line, the information stored in the storage capacitor is read out.
In currently-used DRAM memory cells, the storage capacitor is implemented as a trench capacitor in which the two capacitor electrodes are disposed in a trench that extends into the substrate in a direction perpendicular to the substrate surface. According to another implementation of DRAM memory cell, the electrical charge is stored in a stacked capacitor which is formed above the surface of the substrate.
The access transistor is, for example, implemented as a planar transistor, in which the channel extends horizontally along the surface of the semiconductor substrate.
A known DRAM cell has a grooved transistor in which the gate electrode is disposed in a groove that extends in the substrate. Thereby, a current flowing from the first to the second source/drain regions and vice versa has horizontal and vertical components perpendicular to the substrate surface. This is further described in “The Breakthrough in data retention time of DRAM using Recess-Channel-Array transistor (RCAT) for 88 nm feature size and beyond”, J. Y. Kim et al., 2003 Symposium on VLSI Technology Dig. of Tech. Papers. A further improvement of this transistor is also known.
In particular, US Pat. Appl. US 2005/0020086 A1 discloses a transistor comprising a gate electrode which is formed in a gate groove. In particular, inner sidewall spacers are provided which are formed on sidewalls of the recessed trench so that the center portion of the gate has a smaller width than an upper portion and a lower portion of the gate electrode. By including the sidewall spacers, the influence of the gate electrode on the first and second source/drain regions can be reduced, resulting in a reduced leakage current. However, due to the smaller width of the center portion of the gate electrode, the problem arises, that a contact resistance between the upper portion and the lower portion of the gate electrode and, in particular, the resistance between the corresponding word line and the lower portion of the gate electrode is increased, resulting in a degraded speed performance.
A method of forming special contact plugs is also known.
Memory devices usually comprise a memory cell array and a peripheral portion. The peripheral portion includes support circuitry for operating the memory cell array and, in particular, sense amplifiers and word line drivers.